A semiconductor device package typically comprises a lead frame, a semiconductor die, and an encapsulating package body. The lead frame comprises a base die paddle, lead terminals and tie bars, where the tie bars may or may not mechanically support the base die paddle and the lead terminals.
High power semiconductor devices of about 30 volts to about 1000 volts or higher operate at very high temperatures. Typically, encapsulated high power semiconductor devices, for example, power metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), silicon controlled rectifiers (SCRs), etc., are provided in non-isolated packages. Conventional packaging of encapsulated non-isolated high power semiconductor devices, for example, a MOSFET comprising three lead terminals, namely, a gate lead terminal, a source lead terminal, and a drain lead terminal, comprise connecting one of the lead terminals, for example, the drain lead terminal of the MOSFET to a base metal of the package on which the high power semiconductor device is mounted. When connected in this manner, very high voltages develop at the base metal which presents a hazardous situation to both the high power semiconductor device as well as working personnel operating in such an environment. Furthermore, this method of packaging limits the choices available for configuring the interconnections of the lead terminals. Therefore, there is a need for a method of packaging a power semiconductor device that allows flexible configuration of the lead terminal interconnections.
Most discrete power semiconductor devices are plastic encapsulated using a strip form lead frame constructed such that at least one of the terminals is connected to the base die paddle where the power semiconductor device is mounted. Since the base die paddle is electrically connected to the power semiconductor device, typically to the drain side of the power semiconductor device, the power semiconductor device is mounted on an external heat sink using an insulation pad to avoid an electrical hazard to the power semiconductor devices and packages as well as personnel working on the power semiconductor devices and packages. Conventionally, insulating pads are used to provide isolation between the external heat sink and the power semiconductor device and also to provide thermal coupling from the power semiconductor device to the external heat sink to prevent over-heating and early device failure. However, in practice, there is a certain trade-off while deciding between good thermal coupling and electrical isolation, since adding electrical isolation results in an increase in thermal resistance which deprecates thermal coupling.
Typical applications of packaged power semiconductors require electrical isolation of the external base die paddle, where the drain side of the power semiconductor device is electrically mounted to an external heat sink and to the rest of the circuits. Due to the high voltage present on packaged power semiconductor devices, electrical isolation is required to provide safety to personnel working on the electronic circuit as well as to prevent damage to other electrical components. Power semiconductor devices also generate excessive heat which needs to be dissipated.
Conventionally, thermal tape or other insulating pads are used between the packaged power semiconductor devices and the external heat sink to provide the necessary electrical isolation as well as thermal coupling for heat dissipation. This standard device mounting technique is typically a compromise between the two requirements; that is electrical isolation and thermal coupling. Hence, there is a need for effective thermal coupling as well as electrical isolation between the base die paddles of the packaged power semiconductor device to that of the external heat sink that dissipates the heat generated by the power semiconductor device.
Typical isolated high power semiconductor device packages utilize a direct copper bonded substrate for providing electrical isolation and thermal coupling. One surface of the direct copper bonded substrate is utilized as the base die paddle and multiple lead terminals are coupled to the surface of the direct copper bonded substrate. The opposing surface of the direct copper bonded substrate acts as an external metal for thermal coupling during mounting applications. Such packages are rendered expensive and less effective as these packages require multiple soldering joints on the lead terminals to construct a basic lead frame. Moreover, soldering multiple lead terminals to the lead frame necessitates critical alignment fixtures and elaborate jig that increase the cost of manufacture of such a lead frame. Furthermore, this arrangement further reduces lead terminal design options once the lead terminal assignment changes with respect to the power semiconductor devices.
High power modules, for example, power rectifiers typically exceed the performance limits of readily available packages, for example, TO247, TO264, and TO268 packages. The “TO” designation refers to transistor outline. Such packages for power modules are constructed by assembly of separate base die paddle and lead terminals. In such a construction, the semiconductor die is typically soldered to a non-standard base die paddle and separate lead terminals are mounted using a solder paste. An encapsulating package body of, for example, a plastic material envelops the semiconductor die while exposing the lead terminals and the base metal. A coating, for example, of dielectric or resin material, is applied as a final encapsulation for the power semiconductor device. This power module assembly is expensive due to manual operations required as well as the high cost of non-standard materials and processes. Packaging using this method is also unreliable due to weak encapsulation of the semiconductor die and higher penetration of moisture to the packaged power semiconductor device. There is a need for a method of packaging semiconductor devices that allows integration of power modules into existing packaging standards and permits configuring the power semiconductor devices according to required applications with increased design options.
Hence, there is a long felt but unresolved need for a method for packaging one or more power semiconductor devices that increases power handling and current sinking capabilities of the power semiconductor devices, allows integration into existing packaging standards, reduces labor costs and can be easily constructed from current tooling methodologies, permits configuring according to required applications with increased design options, and ensures safety of personnel involved in operations of such high power semiconductor devices.